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There are two configuration methods, depending on the PCI chipsets used: br /br /Configuration Type 1: br /br /CF8h D(R/W): br /bitnbsp; nbsp;0-7nbsp; Index into the configuration space to read/write at CFCh br /nbsp; nbsp; 11-15nbsp; Card ID (0 - 31) br /nbsp; nbsp; 16-19nbsp; PCI Bus ID (0 - 15) br /nbsp; nbsp; nbsp; nbsp;31nbsp; Set to enable the PCI bus configuration space br /br /CFCh D(R/W): br /bitnbsp; 0-31nbsp; The index register identified by the PCI bus/card ID/Index in CF8h br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;can be accessed here. br /br /br /Configuration Type 2: br /br /CF8h (R/W): br /bitnbsp; nbsp;7nbsp; Set to select the PCI configuration space br /br /CFAh (R/W): br /bit 0-?nbsp; Bus select ? br /br /br /Finding the PCI devices: br /br /nbsp; PCItype:=0; br /nbsp; outp($CF8,0); br /nbsp; outp($CFA,0); br /nbsp; if (inp($CF8)=0) and (inp($CFA)=0) then PCItype:=2 br /nbsp; else begin br /nbsp; nbsp; tmp=inpl($CF8); br /nbsp; nbsp; outpl($CF8,$80000000); br /nbsp; nbsp; if inpl($CF8)=$80000000 then PCItype:=1; br /nbsp; nbsp; outpl($CF8,tmp); br /nbsp; end; br /nbsp; case PCItype of br /nbsp; nbsp; 1:beginnbsp; nbsp;{PCI type 1} br /nbsp; nbsp; nbsp; nbsp; for i:=0 to 511 do br /nbsp; nbsp; nbsp; nbsp; begin br /nbsp; nbsp; nbsp; nbsp; nbsp; outpl($CF8,$80000000+i*longint(2048)); br /nbsp; nbsp; nbsp; nbsp; nbsp; tmp:=inpl($CFC); br /nbsp; nbsp; nbsp; nbsp; nbsp; if ((tmp and $FFFF)lt;gt;$FFFF) and ((tmp shr 16)lt;gt;$FFFF) then br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; _PCI Device: Vendor: (l and $FFFF)nbsp; Device: (l shr 16)_ br /nbsp; nbsp; nbsp; nbsp; end; br /nbsp; nbsp; nbsp; end; br /nbsp; nbsp; 2:beginnbsp; nbsp;{PCI type 2} br /nbsp; nbsp; nbsp; nbsp; outp($CF8,$80); br /nbsp; nbsp; nbsp; nbsp; outp($CFA,0);nbsp; nbsp;{Bus select?} br /nbsp; nbsp; nbsp; nbsp; for i:=0 to 15 do br /nbsp; nbsp; nbsp; nbsp; begin br /nbsp; nbsp; nbsp; nbsp; nbsp; tmp:=inpl(i*256 +$C000); br /nbsp; nbsp; nbsp; nbsp; nbsp; if ((tmp and $FFFF)lt;gt;$FFFF) and ((tmp shr 16)lt;gt;$FFFF) then br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; _PCI Device: Vendor: (l and $FFFF)nbsp; Device: (l shr 16)_ br /nbsp; nbsp; nbsp; nbsp; end; br /nbsp; nbsp; nbsp; nbsp; outp($CF8,0); br /nbsp; nbsp; nbsp; end; br /nbsp; end; br /br /br /The PCI BIOS interface requires a 386 or better CPU. br /br /br /--------X-1AB001----------------------------- br /INT 1A - ? PCI ? - INSTALLATION CHECK br /nbsp; nbsp; nbsp; nbsp; AX = B001h br /Return: CF clear if installed br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; DX = 4350h ('CP') br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; CX = 2049h (' I') br /--------X-1AB002----------------------------- br /INT 1A - ? PCI ? - FIND PCI DEVICE br /nbsp; nbsp; nbsp; nbsp; AX = B002h br /nbsp; nbsp; nbsp; nbsp; CX = device ID br /nbsp; nbsp; nbsp; nbsp; DX = vendor ID br /nbsp; nbsp; nbsp; nbsp; SI = device index (0-n) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 func) br /--------X-1AB00A----------------------------- br /INT 1A - ? PCI ? - READ CONFIGURATION DWORD br /nbsp; nbsp; nbsp; nbsp; AX = B00Ah br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; nbsp; CX = Low 16 bit of the DWORD br /nbsp; nbsp; nbsp; nbsp; nbsp; DX = High 16 bit of the DWORD br /br /--------X-1AB101----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - INSTALLATION CHECK br /nbsp; nbsp; nbsp; nbsp; AX = B101h br /Return: AH = 00h if installed br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; CF clear br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; EDX = 20494350h (' ICP') br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; EDI = physical address of protected-mode entry point (see #0528) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; AL = PCI hardware characteristics (see #0527) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BH = PCI interface level major version (BCD) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BL = PCI interface level minor version (BCD) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; CL = number of last PCI bus in system br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Note:nbsp; nbsp;this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call br /br /Bitfields for PCI hardware characteristics: br /Bit(s)nbsp; Description (Table 0527) br /nbsp;0nbsp; nbsp; nbsp; configuration space access mechanism 1 supported br /nbsp;1nbsp; nbsp; nbsp; configuration space access mechanism 2 supported br /nbsp;2-3nbsp; nbsp; reserved br /nbsp;4nbsp; nbsp; nbsp; Special Cycle generation mechanism 1 supported br /nbsp;5nbsp; nbsp; nbsp; Special Cycle generation mechanism 2 supported br /nbsp;6-7nbsp; nbsp; reserved br /br /(Table 0528) br /Call protected-mode entry point with: br /nbsp; nbsp; nbsp; nbsp; registers as for real/V86-mode INT call br /nbsp; nbsp; nbsp; nbsp; CS = ring 0 descriptor with access to full address space br /Return: as for real/V86-mode call br /--------X-1AB102----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - FIND PCI DEVICE br /nbsp; nbsp; nbsp; nbsp; AX = B102h br /nbsp; nbsp; nbsp; nbsp; CX = device ID br /nbsp; nbsp; nbsp; nbsp; DX = vendor ID br /nbsp; nbsp; nbsp; nbsp; SI = device index (0-n) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 func) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 83h bad vendor ID br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 86h device not found br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call device ID FFFFh br /nbsp; nbsp; nbsp; nbsp; may be reserved as a wildcard in future implementations the meanings of br /nbsp; nbsp; nbsp; nbsp; BL and BH on return were exchanged between the initial drafts of the br /nbsp; nbsp; nbsp; nbsp; specification and final implementation all devices sharing a single br /nbsp; nbsp; nbsp; nbsp; vendor ID and device ID may be enumerated by incrementing SI from 0 br /nbsp; nbsp; nbsp; nbsp; until error 86h is returned br /--------X-1AB103----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - FIND PCI CLASS CODE br /nbsp; nbsp; nbsp; nbsp; AX = B103h br /nbsp; nbsp; nbsp; nbsp; ECX = class code (bits 23-0) br /nbsp; nbsp; nbsp; nbsp; SI = device index (0-n) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 func) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 86h device not found br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation all devices sharing the br /nbsp; nbsp; nbsp; nbsp; same Class Code may be enumerated by incrementing SI from 0 until br /nbsp; nbsp; nbsp; nbsp; error 86h is returned br /--------X-1AB106----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - PCI BUS-SPECIFIC OPERATIONS br /nbsp; nbsp; nbsp; nbsp; AX = B106h br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; EDX = Special Cycle data br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 81h unsupported function br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Note:nbsp; nbsp;this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call br /--------X-1AB108----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION BYTE br /nbsp; nbsp; nbsp; nbsp; AX = B108h br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;CL = byte read br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation br /--------X-1AB109----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION WORD br /nbsp; nbsp; nbsp; nbsp; AX = B109h br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; CX = word read br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation br /--------X-1AB10A----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION DWORD br /nbsp; nbsp; nbsp; nbsp; AX = B10Ah br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; ECX = dword read br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes: this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp;interrupts if they were disabled before making the call the meanings of br /nbsp; nbsp; nbsp; nbsp;BL and BH on return were exchanged between the initial drafts of the br /nbsp; nbsp; nbsp; nbsp;specification and final implementation br /--------X-1AB10B----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION BYTE br /nbsp; nbsp; nbsp; nbsp; AX = B10Bh br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /nbsp; nbsp; nbsp; nbsp; CL = byte to write br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation br /--------X-1AB10C----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION WORD br /nbsp; nbsp; nbsp; nbsp; AX = B10Ch br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (multiple of 2 less than 0100h) br /nbsp; nbsp; nbsp; nbsp; CX = word to write br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation br /--------X-1AB10D----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION DWORD br /nbsp; nbsp; nbsp; nbsp; AX = B10Dh br /nbsp; nbsp; nbsp; nbsp; BH = bus number br /nbsp; nbsp; nbsp; nbsp; BL = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (multiple of 4 less than 0100h) br /nbsp; nbsp; nbsp; nbsp; ECX = dword to write br /Return: CF clear if successful br /nbsp; nbsp; nbsp; nbsp; CF set on error br /nbsp; nbsp; nbsp; nbsp; AH = status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 00h successful br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 87h bad register number br /nbsp; nbsp; nbsp; nbsp; EAX, EBX, ECX, and EDX may be modified br /nbsp; nbsp; nbsp; nbsp; all other flags (except IF) may be modified br /Notes:nbsp; this function may require up to 1024 byte of stack; it will not enable br /nbsp; nbsp; nbsp; nbsp; interrupts if they were disabled before making the call the meanings br /nbsp; nbsp; nbsp; nbsp; of BL and BH on return were exchanged between the initial drafts of br /nbsp; nbsp; nbsp; nbsp; the specification and final implementation br /--------X-1AB181----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - INSTALLATION CHECK (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B181h br /Return: as for AX=B101h br /--------X-1AB182----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - FIND PCI DEVICE (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B182h br /nbsp; nbsp; nbsp; nbsp; CX = device ID br /nbsp; nbsp; nbsp; nbsp; DX = vendor ID br /nbsp; nbsp; nbsp; nbsp; SI = device index (0-n) br /Return: as for AX=B102h br /--------X-1AB183----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - FIND PCI CLASS CODE (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B183h br /nbsp; nbsp; nbsp; nbsp; ECX = class code (bits 23-0) br /nbsp; nbsp; nbsp; nbsp; SI = device index (0-n) br /Return: as for AX=B103h br /--------X-1AB186----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - PCI BUS-SPECIFIC OPERATIONS (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B186h br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; EDX = Special Cycle data br /Return: as for AX=B106h br /--------X-1AB188----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION BYTE (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B188h br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: as for AX=B108h br /--------X-1AB189----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION WORD (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B189h br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: as for AX=B109h br /--------X-1AB18A----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION DWORD (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B18Ah br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /Return: as for AX=B10Ah br /--------X-1AB18B----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION BYTE (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B18Bh br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (0000h-00FFh) br /nbsp; nbsp; nbsp; nbsp; CL = byte to write br /Return: as for AX=B10Bh br /--------X-1AB18C----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION WORD (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B18Ch br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (multiple of 2 less than 0100h) br /nbsp; nbsp; nbsp; nbsp; CX = word to write br /Return: as for AX=B10Ch br /--------X-1AB18D----------------------------- br /INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION DWORD (32-bit) br /nbsp; nbsp; nbsp; nbsp; AX = B18Dh br /nbsp; nbsp; nbsp; nbsp; BL = bus number br /nbsp; nbsp; nbsp; nbsp; BH = device/function number (bits 7-3 device, bits 2-0 function) br /nbsp; nbsp; nbsp; nbsp; DI = register number (multiple of 4 less than 0100h) br /nbsp; nbsp; nbsp; nbsp; ECX = dword to write br /Return: as for AX=B10Dh br /br /br /br /The PCI configuration space consists of 256bytes per device, the first 64 br /bytes are laid out as follows, though an adapter may not implement all fields. br /br /Offsetnbsp; Sizenbsp; nbsp; Description: br /nbsp; 00hnbsp; nbsp;WORDnbsp; nbsp; Vendor ID. FFFFh is reserved. br /nbsp; 02hnbsp; nbsp;WORDnbsp; nbsp; Device ID. FFFFh is reserved. br /nbsp; 04hnbsp; nbsp;WORDnbsp; nbsp; System Bus Command br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bit 0nbsp; I/O Space. If set the device is allowed to respond to br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;I/O requests, if clear the device does not respond. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 1nbsp; Memory Space. If set the device is allowed to respond br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;to Meory requests, if clear the device does not br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;respond. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 3nbsp; Special Cycles. If set the device is allowed to monitor br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;special cycles. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 5nbsp; VGA Palette Snoop. If set special snooping behavior is br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;enabled. The device must not respond to DAC writes. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;If clear palette accesses are treated normally. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 6nbsp; Parity Error. If set the device responds to parity br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;errors, if clear it ignores them. The device must br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;generate parity even if this bit is clear. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 7nbsp; Wait Cycle Control. If set data/address stepping is br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;enabled, disabled if clear. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 8nbsp; System Error Driver. If set the error driver reports br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;parity errors, if clear the system error driver is br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;disconnected. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 9nbsp; Back-to-Back Cycle. If set the device supports back-to br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; -back cycles. br /nbsp; 06hnbsp; nbsp;WORDnbsp; nbsp; System Bus Status br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bit 7nbsp; (R) Fast back-to-back. If set the device is capable of br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;fast back-to-back cycles, if clear it is not. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 8nbsp; Bus Master. Only implemented by Bus Masters br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;9-10nbsp; (R) Device Select Timing. DEVSEL# timing. 0: fast, br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1: medium, 2: slow br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;11nbsp; Device Target-abort. Set whenever the device (as target) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;issues a Target Abort. Write 1 to reset. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;12nbsp; Received Target-abort. Set whenever the device (as br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;Master) receives a Target Abort. Write 1 to reset. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;13nbsp; Master Abort Status. Set whenever the device issues a br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;Master Abort. Write 1 to reset. br /nbsp; 08hnbsp; nbsp;BYTEnbsp; nbsp; Revision Code. br /nbsp; 09hnbsp; nbsp;BYTEnbsp; nbsp; Programming Interface. br /nbsp; 0Ahnbsp; nbsp;WORDnbsp; nbsp; Class. 300h for VGA devices, 1 for 8514/A devices br /nbsp; 0Chnbsp; nbsp;BYTEnbsp; nbsp; Cache line size br /nbsp; 0Dhnbsp; nbsp;BYTEnbsp; nbsp; Latency timer. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bit 0-2nbsp; (R) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 3-7 br /nbsp; 0Ehnbsp; nbsp;BYTEnbsp; nbsp; Header type br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bit 0-6nbsp; Current offset for configuration register ? br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 7nbsp; Multifunction Device? br /nbsp; 0Fhnbsp; nbsp;BYTEnbsp; nbsp; Bist? br /nbsp; 10hnbsp; nbsp;DWORDnbsp; nbsp;Base0 - Defines a Memory or I/O region used by the device br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bitnbsp; 0nbsp; (R) Memory or I/O. Set if the region is in I/O space, br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; clear if it is in Memory space. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1-2nbsp; (R) Locatable Area. 0: Anywhere in 32bit address space br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1: Below 1MB, 2: anywhere in 64bit address space br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;3nbsp; (R) Pre-fetchable. Set if memory is cacheable, clear br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; if not. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;4-7nbsp; (R) Address space size br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 8-31nbsp; Memory Base. Upper 24bit of the base address. br /nbsp; 14hnbsp; nbsp;DWORDnbsp; nbsp;Base1 - Similar to Base0 br /nbsp; 18hnbsp; nbsp;DWORDnbsp; nbsp;Base2 - Similar to Base0 br /nbsp; 1Chnbsp; nbsp;DWORDnbsp; nbsp;Base3 - Similar to Base0 br /nbsp; 20hnbsp; nbsp;DWORDnbsp; nbsp;Base4 - Similar to Base0 br /nbsp; 24hnbsp; nbsp;DWORDnbsp; nbsp;Base5 - Similar to Base0 br /nbsp; 28hnbsp; nbsp;DWORDnbsp; nbsp;Reserved br /nbsp; 2Chnbsp; nbsp;DWORDnbsp; nbsp;Reserved br /nbsp; 30hnbsp; nbsp;DWORDnbsp; nbsp;ROM Base - Defines the location amp; size of the BIOS ROM br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Bitnbsp; nbsp;0nbsp; ROM BIOS Decode. Set to enable BIOS access br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 11-14nbsp; (R) ROM BIOS Min Size. br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;0:nbsp; 32K ROM (bits 15-17 R/W) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1:nbsp; 64K ROM (bits 15 RO, 16-17 R/W) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;2: 128K ROM (bits 15-16 RO, 17 R/W) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;3: 256K ROM (bits 15-17 RO) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; 15-31nbsp; BIOS Base Address. Upper 14-17 bits of the BIOS br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;location. Depending on the BIOS size in bits 11-14 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;the lowest 1/2/3 bits may be forced to 0. br /nbsp; 34hnbsp; nbsp;DWORDnbsp; nbsp;Reserved br /nbsp; 38hnbsp; nbsp;DWORDnbsp; nbsp;Reserved br /nbsp; 3Chnbsp; nbsp;BYTEnbsp; nbsp; Interrupt Line br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Used for Interrupt Line info during initialisation br /nbsp; 3Dhnbsp; nbsp;BYTEnbsp; nbsp; Interrupt Pin br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Identifies the interrupt lines used br /nbsp; 3Ehnbsp; nbsp;BYTEnbsp; nbsp; Minimum Grant br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Specifies the longest burst allowed br /nbsp; 3Fhnbsp; nbsp;BYTEnbsp; nbsp; Max Lat br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Indicates how often the device geta access to the PCI bus. br /br /br /Known Vendor/Device ID combinations: br /Vendor:nbsp; nbsp;Device:nbsp; nbsp; nbsp;Card: br /nbsp;0E11hnbsp; nbsp; nbsp;3032hnbsp; nbsp; nbsp; Compaq QVision 1280P br /nbsp;1000hnbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; NCR br /nbsp;1002hnbsp; nbsp; nbsp;4158hnbsp; nbsp; nbsp; ATI Mach32 (68800-AX) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;4758hnbsp; nbsp; nbsp; ATI Mach64 (88800-GX) br /nbsp;1005hnbsp; nbsp; nbsp;2301hnbsp; nbsp; nbsp; Avance Logic ALG2301 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;2302hnbsp; nbsp; nbsp; Avance Logic ALG2302 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;2364hnbsp; nbsp; nbsp; Avance Logic ALG2364 br /nbsp;100Chnbsp; nbsp; nbsp;3202hnbsp; nbsp; nbsp; Tseng ET4000/W32p revA br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;3207hnbsp; nbsp; nbsp; Tseng ET4000/W32p revD br /nbsp;100Ehnbsp; nbsp; nbsp;9001hnbsp; nbsp; nbsp; Weitek Viper/PCI br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;9100hnbsp; nbsp; nbsp; Weitek Viper Pro/SE br /nbsp;1011hnbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; Digital br /nbsp;1013hnbsp; nbsp; nbsp;00A0hnbsp; nbsp; nbsp; Cirrus Logic CL-GD5430 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;00A8hnbsp; nbsp; nbsp; Cirrus Logic CL-GD5434 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1200hnbsp; nbsp; nbsp; Cirrus Logic CL-GD7542 (Nordic) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1202hnbsp; nbsp; nbsp; Cirrus Logic CL-GD7543 (Viking) br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;1204hnbsp; nbsp; nbsp; Cirrus Logic CL-GD7541 (Nordic Light) br /nbsp;101Ahnbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; NCR br /nbsp;1023hnbsp; nbsp; nbsp;9420hnbsp; nbsp; nbsp; Trident TGUI9420DGi br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;9430hnbsp; nbsp; nbsp; Trident TGUI9430 br /nbsp;1025hnbsp; nbsp; nbsp;1435hnbsp; nbsp; nbsp; Acer Labs M1435 (huh maybe M3145??) br /nbsp;102Bhnbsp; nbsp; nbsp;0518hnbsp; nbsp; nbsp; Matrox ? br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;0D10hnbsp; nbsp; nbsp; Matrox Impression Plus br /nbsp;102Chnbsp; nbsp; nbsp;00B8hnbsp; nbsp; nbsp; Chipsamp;Tech CT64310 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;00D8hnbsp; nbsp; nbsp; Chipsamp;Tech CT65545 br /nbsp;105Dhnbsp; nbsp; nbsp;2309hnbsp; nbsp; nbsp; Number Nine (#9) Imagine-128 br /nbsp;1060hnbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; nbsp; UMC br /nbsp;1142hnbsp; nbsp; nbsp;3210hnbsp; nbsp; nbsp; Alliance Pro Motion 3210 br /nbsp;1A08hnbsp; nbsp; nbsp;0000hnbsp; nbsp; nbsp; Sierra 15064 ? br /nbsp;5333hnbsp; nbsp; nbsp;8811hnbsp; nbsp; nbsp; S3 Trio64 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;8880hnbsp; nbsp; nbsp; S3 86c866 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;88B0hnbsp; nbsp; nbsp; S3 86c928P br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;88C0hnbsp; nbsp; nbsp; S3 86c864 br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;88C1hnbsp; nbsp; nbsp; S3 86c864P br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;88D0hnbsp; nbsp; nbsp; S3 86c964 br /nbsp;EDD8hnbsp; nbsp; nbsp;A091hnbsp; nbsp; nbsp; ARK 1000PV br /nbsp; nbsp; nbsp; nbsp; nbsp; nbsp;A099hnbsp; nbsp; nbsp; ARK 2000PV

크리에이티브 커먼즈 라이센스

이 저작물은 크리에이티브 커먼즈 코리아 저작자표시-비영리-동일조건변경허락 2.0 대한민국 라이센스에 따라 이용하실 수 있습니다.